• Core: 16-Bit dsPIC33F
• Code-Efficient (C and Assembly) Architecture
• Two 40-Bit Wide Accumulators
• Single-Cycle (MAC/MPY) with Dual Data Fetch
• Single-Cycle Mixed-Sign MUL plus Hardware Divide
• 32-Bit Multiply Support
• Clock Management
• ±1% Internal Oscillator
• Programmable PLLs and Oscillator Clock Sources
• Fast Wake-up and Start-up
• Power Management
• Low-Power Management modes (Sleep, Idle, Doze)
• Integrated Power-on Reset and Brown-out Reset
• High-Speed PWM
• Up to 9 PWM Pairs with Independent Timing
• Dead Time for Rising and Falling Edges
• 1.04 ns PWM Resolution
• Advanced Analog Features
• High-Speed ADC module: 10-bit resolution with up to two Successive Approximation Register (SAR)
• Timers/Output Compare/Input Capture
• Six General Purpose Timers
• Four Output Compare (OC) modules Configurable as Timers/Counters
• Communication Interfaces
• Two UART modules (12.5 Mbps)
• Two 4-wire SPI modules (15 Mbps)
• ECAN™ module (1 Mbaud) CAN 2.0B Support
• Two I2C™ modules (up to 1 Mbaud) with SMBus Support
• Direct Memory Access (DMA)
• 4-Channel DMA with User-Selectable Priority Arbitration
• UART, SPI, ECAN™, IC, OC and Timers

DSPIC33FJ64GS606T-I/PT属性